1. Field Of the Invention
This invention relates to field effect transistors and processes for making field effect transistors and in particular to processes which use selective removal of sidewall spacers and a portion of an underlying conductive layer to isolate self-aligned source/drain contacts from gates.
2. Description of Related Art
Field effect transistors are common integrated circuit elements having many uses. FIG. 1 shows an example of a prior art field effect transistor 100 having a source 102 and a drain 103 formed in a silicon substrate 101. Substrate 101 contains P-type dopants such as boron, and source 102 and drain 103 are heavily doped with N-type dopants such as arsenic. A channel region 105 of substrate 101 may optionally be lightly doped with N-type dopants to alter the threshold voltage of transistor 100. A polysilicon gate 104 overlies channel region 105 and is separated from substrate 101 by an insulating gate oxide 106. External voltages are applied to source 102 and drain 103 via metal source/drain contacts 122 and 123 and polysilicon source/drain contacts 112 and 113.
Manufacturing constraints limit the minimum size of transistor 100. For example, for an operable transistor, polysilicon contacts 112 and 113 must be separated from gate 104. If gate 104 and contacts 105 are formed using two separate masks, the designed separations between gate 104 and contacts 112 and 113 must be large enough to accommodate expected misalignment between masks. The potential for misalignment requires that active regions 102 and 103 in substrate 101 be larger than the minimal operable size by at least the expected misalignment between masks. Accordingly, manufacturing processes which eliminate misalignment between gate and contact masks could reduce active region size.